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authorLisa Hsu <hsul@eecs.umich.edu>2006-10-30 16:51:46 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2006-10-30 16:51:46 -0500
commit580c8421ab5d438ea4264a3a44495568a38bc59b (patch)
treef9ae5cbebe2e4c3568297b1fa9a058f9a21edc03 /configs/example/fs.py
parentfe2698c435ef8f37273e60f1cc7d70b95b4aa3d5 (diff)
downloadgem5-580c8421ab5d438ea4264a3a44495568a38bc59b.tar.xz
se.py, fs.py:
import Caches Simulation.py: Fix typo - L2Cache --> L1Cache configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches --HG-- extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
Diffstat (limited to 'configs/example/fs.py')
-rw-r--r--configs/example/fs.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index aefa26169..3ce463879 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -35,6 +35,7 @@ from FSConfig import *
from SysPaths import *
from Benchmarks import *
import Simulation
+from Caches import *
if not m5.build_env['FULL_SYSTEM']:
m5.panic("This script requires full-system mode (ALPHA_FS).")
@@ -104,7 +105,7 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np):
if options.caches and not options.standard_switch:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L2Cache(size = '64kB'))
+ L1Cache(size = '64kB'))
test_sys.cpu[i].connectMemPorts(test_sys.membus)
test_sys.cpu[i].mem = test_sys.physmem