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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
| commit | 95a0b184314cf0171a20fb7e71c845891dc56496 (patch) | |
| tree | 00590e68aa9d66c225a8f0d08f82eca2771e461d /configs/example/fs.py | |
| parent | 8ccfd9defa930d5c2904134d7a7286682e721db9 (diff) | |
| download | gem5-95a0b184314cf0171a20fb7e71c845891dc56496.tar.xz | |
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.
Diffstat (limited to 'configs/example/fs.py')
| -rw-r--r-- | configs/example/fs.py | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 19a2bd358..abf8fe966 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -135,7 +135,10 @@ def build_test_system(np): print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) - Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) + Ruby.create_system(options, True, test_sys, test_sys.iobus, + test_sys._dma_ports) + test_sys.physmem = [SimpleMemory(range = r, null = True) + for r in test_sys.mem_ranges] # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, @@ -160,13 +163,9 @@ def build_test_system(np): cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master - test_sys.ruby._cpu_ports[i].access_phys_mem = True - - # Create the appropriate memory controllers - # and connect them to the IO bus - test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] - for i in xrange(len(test_sys.mem_ctrls)): - test_sys.mem_ctrls[i].port = test_sys.iobus.master + # Connect the ruby io port to the PIO bus, + # assuming that there is just one such port. + test_sys.iobus.master = test_sys.ruby._io_port.slave else: if options.caches or options.l2cache: |