config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.

1 files changed, 25 insertions, 13 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 028148404..037a54b75 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -102,17 +102,16 @@ else:
 np = options.num_cpus
 
 if buildEnv['TARGET_ISA'] == "alpha":
-    test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "mips":
-    test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "sparc":
-    test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeSparcSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "x86":
-    test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
-                                  options.num_cpus, bm[0])
+    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
 elif buildEnv['TARGET_ISA'] == "arm":
-    test_sys = makeArmSystem(test_mem_mode, options.machine_type,
-                             TestMemClass, bm[0], options.dtb_filename,
+    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
+                             options.dtb_filename,
                              bare_metal=options.bare_metal)
 else:
     fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
@@ -164,18 +163,24 @@ for i in xrange(np):
 
 CacheConfig.config_cache(options, test_sys)
 
+# Create the appropriate memory controllers and connect them to the
+# memory bus
+test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
+                      for r in test_sys.mem_ranges]
+for i in xrange(len(test_sys.mem_ctrls)):
+    test_sys.mem_ctrls[i].port = test_sys.membus.master
+
 if len(bm) == 2:
     if buildEnv['TARGET_ISA'] == 'alpha':
-        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'mips':
-        drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'sparc':
-        drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'x86':
-        drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
+        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
     elif buildEnv['TARGET_ISA'] == 'arm':
-        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
-                                  DriveMemClass, bm[1])
+        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
 
     # Create a source clock for the system and set the clock period
     drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
@@ -201,6 +206,13 @@ if len(bm) == 2:
     drive_sys.iobridge.slave = drive_sys.iobus.master
     drive_sys.iobridge.master = drive_sys.membus.slave
 
+    # Create the appropriate memory controllers and connect them to the
+    # memory bus
+    drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
+                           for r in drive_sys.mem_ranges]
+    for i in xrange(len(drive_sys.mem_ctrls)):
+        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
+
     drive_sys.init_param = options.init_param
     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1: