diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-10 16:26:34 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-10 16:26:34 +0100 |
| commit | eb87ed8e7458c3214d4163a7dbb180110b375d98 (patch) | |
| tree | 1b7bbcc63be9c1e89460dccdef250bed67fb5830 /configs/example/fs.py | |
| parent | f540f1a23012807394f8b9f52a7fd57288f4df9c (diff) | |
| download | gem5-eb87ed8e7458c3214d4163a7dbb180110b375d98.tar.xz | |
arm, config: Add initial support for Ruby
Add initial support for creating an ARM system with a Ruby-based
memory system. This support is currently experimental and limited to
the new VExpress_GEM5_V1 platform.
Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Diffstat (limited to 'configs/example/fs.py')
| -rw-r--r-- | configs/example/fs.py | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 6ee969a6e..a916ca49f 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010-2013 ARM Limited +# Copyright (c) 2010-2013, 2016 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -99,7 +99,8 @@ def build_test_system(np): options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, - external_memory=options.external_memory_system) + external_memory=options.external_memory_system, + ruby=options.ruby) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: @@ -172,10 +173,11 @@ def build_test_system(np): cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave - if buildEnv['TARGET_ISA'] == "x86": + if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave + if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master |