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| author | Andreas Hansson <andreas.hansson> | 2013-07-18 08:31:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson> | 2013-07-18 08:31:19 -0400 |
| commit | c20105c2ff2b8300fa18a5c3f1afb806d6ae9458 (patch) | |
| tree | c417dc17fae5bf5a9862536870101c58db9aa87b /configs/example/memtest.py | |
| parent | d4273cc9a6f3c00566e97ebcd71509ed14477b37 (diff) | |
| download | gem5-c20105c2ff2b8300fa18a5c3f1afb806d6ae9458.tar.xz | |
config: Update script to set cache line size on system
This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.
Diffstat (limited to 'configs/example/memtest.py')
| -rw-r--r-- | configs/example/memtest.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index a74f4b2f3..65f3ec315 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -109,7 +109,7 @@ if len(treespec) < 1: sys.exit(1) # define prototype L1 cache -proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size, +proto_l1 = BaseCache(size = '32kB', assoc = 4, hit_latency = '1ns', response_latency = '1ns', tgts_per_mshr = 8) @@ -143,7 +143,8 @@ for scale in treespec[:-2]: # system simulated system = System(funcmem = SimpleMemory(in_addr_map = False), funcbus = NoncoherentBus(), - physmem = SimpleMemory(latency = "100ns")) + physmem = SimpleMemory(latency = "100ns"), + cache_line_size = block_size) system.clk_domain = SrcClockDomain(clock = options.sys_clock) def make_level(spec, prototypes, attach_obj, attach_port): |