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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-08-21 07:03:23 -0400 |
| commit | ddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch) | |
| tree | 89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /configs/example/memtest.py | |
| parent | d71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff) | |
| download | gem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz | |
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.
--HG--
rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'configs/example/memtest.py')
| -rw-r--r-- | configs/example/memtest.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index a51bd2796..08f134533 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -175,9 +175,9 @@ else: sys.exit(1) # Define a prototype L1 cache that we scale for all successive levels -proto_l1 = BaseCache(size = '32kB', assoc = 4, - hit_latency = 1, response_latency = 1, - tgts_per_mshr = 8) +proto_l1 = Cache(size = '32kB', assoc = 4, + hit_latency = 1, response_latency = 1, + tgts_per_mshr = 8) if options.blocking: proto_l1.mshrs = 1 |