mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.

--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh

1 files changed, 2 insertions, 2 deletions

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index feeffa764..eaf3a52bd 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -147,7 +147,7 @@ for scale in treespec[:-2]:
 
 # system simulated
 system = System(funcmem = SimpleMemory(in_addr_map = False),
-                funcbus = NoncoherentBus(),
+                funcbus = NoncoherentXBar(),
                 physmem = SimpleMemory(latency = "100ns"),
                 cache_line_size = block_size)
 
@@ -162,7 +162,7 @@ def make_level(spec, prototypes, attach_obj, attach_port):
      parent = attach_obj # use attach obj as config parent too
      if len(spec) > 1 and (fanout > 1 or options.force_bus):
           port = getattr(attach_obj, attach_port)
-          new_bus = CoherentBus(width=16)
+          new_bus = CoherentXBar(width=16)
           if (port.role == 'MASTER'):
                new_bus.slave = port
                attach_port = "master"