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authorMitch Hayenga <mitch.hayenga+gem5@gmail.com>2013-04-23 09:47:52 -0400
committerMitch Hayenga <mitch.hayenga+gem5@gmail.com>2013-04-23 09:47:52 -0400
commitb222ba2fd32c5ac9c91cfab518382761cac5b2c7 (patch)
tree09e3dddac2413aa7cf6ea4b58faab9a7bd4708d4 /configs/example/ruby_fs.py
parent3e35fa5dcc8af49f652a20595ce2470b5a116ddc (diff)
downloadgem5-b222ba2fd32c5ac9c91cfab518382761cac5b2c7.tar.xz
sim: Fix two bugs relating to software caching of PageTable entries.
The existing implementation can read uninitialized data or stale information from the cached PageTable entries. 1) Add a valid bit for the cache entries. Simply using zero for the virtual address to signify invalid entries is not sufficient. Speculative, wrong-path accesses frequently access page zero. The current implementation would return a uninitialized TLB entry when address zero was accessed and the PageTable cache entry was invalid. 2) When unmapping/mapping/remaping a page, invalidate the corresponding PageTable cache entry if one already exists.
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