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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-02-06 17:21:18 -0800 |
| commit | dc8018a5c3482008232e6faaa2d96cf20aed7485 (patch) | |
| tree | a972ac4544e227397595baf6eeb30e1854f480fc /configs/example/ruby_mem_test.py | |
| parent | c8c82f09a282832d919f7eb073a47be838e65b29 (diff) | |
| download | gem5-dc8018a5c3482008232e6faaa2d96cf20aed7485.tar.xz | |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Diffstat (limited to 'configs/example/ruby_mem_test.py')
| -rw-r--r-- | configs/example/ruby_mem_test.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index e2887410f..b6e153be4 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -142,7 +142,7 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, # artifical delay is randomly inserted on messages # system.ruby.randomization = True - + assert(len(cpus) == len(system.ruby._cpu_ports)) for (i, cpu) in enumerate(cpus): |