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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:41 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 14:32:29 +0800 |
| commit | 31982a0b92803a9eb4d3479732517ccc9d294f92 (patch) | |
| tree | 144a83457598d934a3e8cbbee4ae6b2f9f84e463 /configs/example/se.py | |
| parent | a17658beaacabe018be78c32aafe8415cdb16df0 (diff) | |
| download | gem5-31982a0b92803a9eb4d3479732517ccc9d294f92.tar.xz | |
invisispec-1.0 configs
Diffstat (limited to 'configs/example/se.py')
| -rw-r--r-- | configs/example/se.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 99d79bc57..6433b5d53 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -282,5 +282,9 @@ else: CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) +# [InvisiSpec] Configure simulation scheme +if CPUClass == DerivO3CPU: + CpuConfig.config_scheme(CPUClass, system.cpu, options) + root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass) |