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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:34 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:34 -0400 |
commit | c26911013c799d63dfe854de8cce11137324cde2 (patch) | |
tree | 78146c1582a62407565da5b2bac34581b021015f /configs/example/se.py | |
parent | 49d88f08b0ff463bca04285dca240b3730889a1d (diff) | |
download | gem5-c26911013c799d63dfe854de8cce11137324cde2.tar.xz |
config: Command line support for multi-channel memory
This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.
The se/fs.py example scripts are updated to make use of the new
feature.
Diffstat (limited to 'configs/example/se.py')
-rw-r--r-- | configs/example/se.py | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 39572cd86..02a0d3b96 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -58,6 +58,7 @@ import Options import Ruby import Simulation import CacheConfig +import MemConfig from Caches import * from cpu2000 import * @@ -157,8 +158,8 @@ if options.smt and options.num_cpus > 1: np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], - physmem = MemClass(range=AddrRange(options.mem_size)), mem_mode = test_mem_mode, + mem_ranges = [AddrRange(options.mem_size)], cache_line_size = options.cacheline_size) # Create a top-level voltage domain @@ -221,7 +222,8 @@ if options.ruby: sys.exit(1) # Set the option for physmem so that it is not allocated any space - system.physmem.null = True + system.physmem = MemClass(range=AddrRange(options.mem_size), + null = True) options.use_map = True Ruby.create_system(options, system) @@ -247,8 +249,8 @@ if options.ruby: else: system.membus = CoherentBus() system.system_port = system.membus.slave - system.physmem.port = system.membus.master CacheConfig.config_cache(options, system) + MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass) |