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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:41 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-05-31 15:59:08 +0800 |
| commit | df8a5016d82e2c85e96f99eeff30d9a963cecffe (patch) | |
| tree | d780d3710302c7835e295406df3ff2cd3b4c77e6 /configs/example/se.py | |
| parent | a4c6e88d766858b675a7fd256df5a8b9a7e18ada (diff) | |
| download | gem5-df8a5016d82e2c85e96f99eeff30d9a963cecffe.tar.xz | |
invisispec-1.0 configs and exp script
import from original code: https://github.com/mjyan0720/InvisiSpec-1.0
Diffstat (limited to 'configs/example/se.py')
| -rw-r--r-- | configs/example/se.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 8403066f0..35652c00b 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -270,5 +270,9 @@ else: CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) +# [InvisiSpec] Configure simulation scheme +if CPUClass == DerivO3CPU: + CpuConfig.config_scheme(CPUClass, system.cpu, options) + root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass) |