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author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
commit | 279f179babc9e5663156777c533c06edc91bce9a (patch) | |
tree | e6718ee514cc81678491b50562ce8c463c0b20fd /configs/example/se.py | |
parent | 5aa104e072eb20f6aca49b169521b0c2da33c844 (diff) | |
parent | 295516a590b6e47c9a881f193027447e500c749c (diff) | |
download | gem5-279f179babc9e5663156777c533c06edc91bce9a.tar.xz |
merge
Diffstat (limited to 'configs/example/se.py')
-rw-r--r-- | configs/example/se.py | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 67a2340ce..c490ed6b6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -30,15 +30,21 @@ # # "m5 test.py" +import os +import optparse +import sys +from os.path import join as joinpath + import m5 +from m5.defines import buildEnv +from m5.objects import * +from m5.util import addToPath, fatal -if m5.build_env['FULL_SYSTEM']: - m5.fatal("This script requires syscall emulation mode (*_SE).") +if buildEnv['FULL_SYSTEM']: + fatal("This script requires syscall emulation mode (*_SE).") + +addToPath('../common') -from m5.objects import * -import os, optparse, sys -from os.path import join as joinpath -m5.AddToPath('../common') import Simulation from Caches import * from cpu2000 import * @@ -70,7 +76,7 @@ if args: if options.bench: try: - if m5.build_env['TARGET_ISA'] != 'alpha': + if buildEnv['TARGET_ISA'] != 'alpha': print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time" sys.exit(1) exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench) @@ -94,8 +100,9 @@ if options.errout != "": # By default, set workload to path of user-specified binary workloads = options.cmd +numThreads = 1 -if options.detailed: +if options.detailed or options.inorder: #check for SMT workload workloads = options.cmd.split(';') if len(workloads) > 1: @@ -124,11 +131,12 @@ if options.detailed: smt_process.errout = errouts[smt_idx] process += [smt_process, ] smt_idx += 1 - + numThreads = len(workloads) + (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) CPUClass.clock = '2GHz' -CPUClass.numThreads = len(workloads) +CPUClass.numThreads = numThreads; np = options.num_cpus |