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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
| commit | 42ba158479c3feed12335958684200de8b6d2ece (patch) | |
| tree | e16873a83f3571fce483231c57839fcabaad75b0 /configs/example/se.py | |
| parent | 1cfe2c88204aed6310fa8be9a310350cb06f6026 (diff) | |
| download | gem5-42ba158479c3feed12335958684200de8b6d2ece.tar.xz | |
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
The store queue doesn't need to be ISA specific and architectures can
frequently store more than an int registers worth of data. A 128 bits seems
more common, but even 256 bits may be appropriate. Pretty much anything less
than a cache line size is buildable.
Diffstat (limited to 'configs/example/se.py')
0 files changed, 0 insertions, 0 deletions