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author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:13:40 -0800 |
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committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:13:40 -0800 |
commit | a70f70ccbff28e80f247507204fa3d1eff8b1baf (patch) | |
tree | 876ca766760cc1a96b40317858c84e2167bbfd5d /configs/example/se.py | |
parent | ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (diff) | |
download | gem5-a70f70ccbff28e80f247507204fa3d1eff8b1baf.tar.xz |
configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
Diffstat (limited to 'configs/example/se.py')
-rw-r--r-- | configs/example/se.py | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 7c09bcc5c..a249f46dd 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -46,6 +46,7 @@ if buildEnv['FULL_SYSTEM']: addToPath('../common') import Simulation +import CacheConfig from Caches import * from cpu2000 import * @@ -146,21 +147,9 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], system.physmem.port = system.membus.port -if options.l2cache: - system.l2 = L2Cache(size='2MB') - system.tol2bus = Bus() - system.l2.cpu_side = system.tol2bus.port - system.l2.mem_side = system.membus.port - system.l2.num_cpus = np +CacheConfig.config_cache(options, system) for i in xrange(np): - if options.caches: - system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - if options.l2cache: - system.cpu[i].connectMemPorts(system.tol2bus) - else: - system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process if options.fastmem: |