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| author | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
|---|---|---|
| committer | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
| commit | ec4000e0e284834df0eb1db792074a1b11f21cc8 (patch) | |
| tree | 9b42b9697c8fe3cf00c3ab8257002146d8d37a9c /configs/example/se.py | |
| parent | 1caed1465470269c36897904edddf8d4dc9765b1 (diff) | |
| download | gem5-ec4000e0e284834df0eb1db792074a1b11f21cc8.tar.xz | |
Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.
--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
Diffstat (limited to 'configs/example/se.py')
| -rw-r--r-- | configs/example/se.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 20fe75a21..639bcd7c6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -114,6 +114,9 @@ for i in xrange(np): system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process + if options.fastmem: + system.cpu[0].physmem_port = system.physmem.port + root = Root(system = system) Simulation.run(options, root, system, FutureClass) |