summaryrefslogtreecommitdiff
path: root/configs/example/se.py
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-11-09 15:06:00 -0500
committerKevin Lim <ktlim@umich.edu>2006-11-09 15:06:00 -0500
commit6591ebb09839586b6849cd28b7c888a2757ba676 (patch)
tree0af7cab23e52bac2529049ec2abf8829479cdd9a /configs/example/se.py
parentf4aa4e43c41fa688abbee9dfa5b2a35a44b2dcf5 (diff)
parent0ba2cc6571f80beb3600000649403cbff0b67d8b (diff)
downloadgem5-6591ebb09839586b6849cd28b7c888a2757ba676.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
Diffstat (limited to 'configs/example/se.py')
-rw-r--r--configs/example/se.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 0a158244f..0944a030e 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
system.physmem.port = system.membus.port
for i in xrange(np):
- if options.caches and not options.standard_switch and not FutureClass:
+ if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
system.cpu[i].connectMemPorts(system.membus)