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| author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:41 +0800 |
|---|---|---|
| committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 16:08:09 +0800 |
| commit | e7938a0d846680320dd01ac1532408aab6b4f51c (patch) | |
| tree | 88603b4dc87833212b47d29c8040e8b0f1c6dee2 /configs/example/se.py | |
| parent | 0ca254aa8381ba2fae61a4a056301e35da9ffab3 (diff) | |
| download | gem5-e7938a0d846680320dd01ac1532408aab6b4f51c.tar.xz | |
invisispec-1.0 configs
Diffstat (limited to 'configs/example/se.py')
| -rw-r--r-- | configs/example/se.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 015a953da..8c457cc9c 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -275,5 +275,9 @@ else: CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) +# [InvisiSpec] Configure simulation scheme +if CPUClass == DerivO3CPU: + CpuConfig.config_scheme(CPUClass, system.cpu, options) + root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass) |