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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /configs/example/se.py | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'configs/example/se.py')
| -rw-r--r-- | configs/example/se.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index afd916cdb..0928482b7 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -265,9 +265,9 @@ if options.ruby: system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': - system.cpu[i].interrupts.pio = ruby_port.master - system.cpu[i].interrupts.int_master = ruby_port.slave - system.cpu[i].interrupts.int_slave = ruby_port.master + system.cpu[i].interrupts[0].pio = ruby_port.master + system.cpu[i].interrupts[0].int_master = ruby_port.slave + system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: |