summaryrefslogtreecommitdiff
path: root/configs/example
diff options
context:
space:
mode:
authorNikos Nikoleris <nikos.nikoleris@arm.com>2018-02-05 09:45:20 +0000
committerNikos Nikoleris <nikos.nikoleris@arm.com>2018-05-31 17:45:23 +0000
commit51056cec69a72931a319e7be9370ea63f18e1aa3 (patch)
tree9ba8760c4b488879674cfa715ac0b5fff1f4b36c /configs/example
parent7d990bd25b478d906442ea63e1de6b381b51817b (diff)
downloadgem5-51056cec69a72931a319e7be9370ea63f18e1aa3.tar.xz
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/memtest.py17
1 files changed, 14 insertions, 3 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index df22609bd..d293164ce 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -83,6 +83,8 @@ parser.add_option("-c", "--caches", type="string", default="2:2:1",
help="Colon-separated cache hierarchy specification, "
"see script comments for details "
"[default: %default]")
+parser.add_option("--noncoherent-cache", action="store_true",
+ help="Adds a non-coherent, last-level cache")
parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
help="Colon-separated tester hierarchy specification, "
"see script comments for details "
@@ -299,10 +301,19 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
# Top level call to create the cache hierarchy, bottom up
make_cache_level(cachespec, cache_proto, len(cachespec), None)
-# Connect the lowest level crossbar to the memory
+# Connect the lowest level crossbar to the last-level cache and memory
+# controller
last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
-last_subsys.xbar.master = system.physmem.port
last_subsys.xbar.point_of_coherency = True
+if options.noncoherent_cache:
+ system.llc = NoncoherentCache(size = '16MB', assoc = 16, tag_latency = 10,
+ data_latency = 10, sequential_access = True,
+ response_latency = 20, tgts_per_mshr = 8,
+ mshrs = 64)
+ last_subsys.xbar.master = system.llc.cpu_side
+ system.llc.mem_side = system.physmem.port
+else:
+ last_subsys.xbar.master = system.physmem.port
root = Root(full_system = False, system = system)
if options.atomic: