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authorNathan Binkert <nate@binkert.org>2007-08-12 09:56:37 -0700
committerNathan Binkert <nate@binkert.org>2007-08-12 09:56:37 -0700
commit64295b800fd67e9b9bb3eee0131511a71ddf1fdb (patch)
treeed1c759f11384dd2c263b43d7842be2922c5c39d /configs/example
parentb92594dd90f54a892771989a8164148e6647c9ab (diff)
parentec4000e0e284834df0eb1db792074a1b11f21cc8 (diff)
downloadgem5-64295b800fd67e9b9bb3eee0131511a71ddf1fdb.tar.xz
merge
--HG-- extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py12
-rw-r--r--configs/example/se.py3
2 files changed, 14 insertions, 1 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index e772a3ab1..3a57fe5b8 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -121,12 +121,20 @@ for i in xrange(np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
-
+ test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+ test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+ test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
+ cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
+ test_sys.iocache.cpu_side = test_sys.iobus.port
+ test_sys.iocache.mem_side = test_sys.membus.port
if options.l2cache:
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
else:
test_sys.cpu[i].connectMemPorts(test_sys.membus)
+ if options.fastmem:
+ test_sys.cpu[i].physmem_port = test_sys.physmem.port
+
if len(bm) == 2:
if m5.build_env['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
@@ -134,6 +142,8 @@ if len(bm) == 2:
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
+ if options.fastmem:
+ drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
diff --git a/configs/example/se.py b/configs/example/se.py
index 20fe75a21..639bcd7c6 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -114,6 +114,9 @@ for i in xrange(np):
system.cpu[i].connectMemPorts(system.membus)
system.cpu[i].workload = process
+ if options.fastmem:
+ system.cpu[0].physmem_port = system.physmem.port
+
root = Root(system = system)
Simulation.run(options, root, system, FutureClass)