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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-27 03:24:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-27 03:24:21 -0400 |
| commit | 9d9b71e485a424bc09e56806cc69d14413a79a48 (patch) | |
| tree | c86229048fad3c7684f31dad8be05fa338a62be0 /configs/example | |
| parent | 91e74beee60b2085d18dfbfd51018dce2c779d8d (diff) | |
| download | gem5-9d9b71e485a424bc09e56806cc69d14413a79a48.tar.xz | |
Configs: Fix memtest.py by moving the system port
The memtest.py script used to connect the system port directly to the
SimpleMemory, but the latter is now single ported. Since the system
port is not used for anything in this particular example, a quick fix
is to attach it to the functional bus instead.
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/memtest.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 4f57ef063..e337fe2b1 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -189,7 +189,7 @@ else: # The system port is never used in the tester so merely connect it # to avoid problems -root.system.system_port = root.system.physmem.port +root.system.system_port = root.system.funcbus.slave # Not much point in this being higher than the L1 latency m5.ticks.setGlobalFrequency('1ns') |