configs: pull out cache configuration code from se.py and fs.py.

Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.

2 files changed, 4 insertions, 26 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 23285e101..c0b434eb3 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -44,6 +44,7 @@ from FSConfig import *
 from SysPaths import *
 from Benchmarks import *
 import Simulation
+import CacheConfig
 from Caches import *
 
 # Get paths we might need.  It's expected this file is in m5/configs/example.
@@ -120,11 +121,7 @@ if options.kernel is not None:
 if options.script is not None:
     test_sys.readfile = options.script
 
-if options.l2cache:
-    test_sys.l2 = L2Cache(size = '2MB')
-    test_sys.tol2bus = Bus()
-    test_sys.l2.cpu_side = test_sys.tol2bus.port
-    test_sys.l2.mem_side = test_sys.membus.port
+CacheConfig.config_cache(options, system)
 
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 
@@ -136,14 +133,6 @@ if options.caches or options.l2cache:
     test_sys.iocache.mem_side = test_sys.membus.port
 
 for i in xrange(np):
-    if options.caches:
-        test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                L1Cache(size = '64kB'))
-    if options.l2cache:
-        test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
-    else:
-        test_sys.cpu[i].connectMemPorts(test_sys.membus)
-
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
 
diff --git a/configs/example/se.py b/configs/example/se.py
index 7c09bcc5c..a249f46dd 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -46,6 +46,7 @@ if buildEnv['FULL_SYSTEM']:
 addToPath('../common')
 
 import Simulation
+import CacheConfig
 from Caches import *
 from cpu2000 import *
 
@@ -146,21 +147,9 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 
 system.physmem.port = system.membus.port
 
-if options.l2cache:
-    system.l2 = L2Cache(size='2MB')
-    system.tol2bus = Bus()
-    system.l2.cpu_side = system.tol2bus.port
-    system.l2.mem_side = system.membus.port
-    system.l2.num_cpus = np
+CacheConfig.config_cache(options, system)
 
 for i in xrange(np):
-    if options.caches:
-        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                              L1Cache(size = '64kB'))
-    if options.l2cache:
-        system.cpu[i].connectMemPorts(system.tol2bus)
-    else:
-        system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
     if options.fastmem: