CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.

2 files changed, 16 insertions, 11 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 19c1bd81f..b3d607a1b 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -152,8 +152,6 @@ test_sys.init_param = options.init_param
 
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 
-CacheConfig.config_cache(options, test_sys)
-
 if bm[0]:
     mem_size = bm[0].mem()
 else:
@@ -171,6 +169,10 @@ else:
 for i in xrange(np):
     if options.fastmem:
         test_sys.cpu[i].physmem_port = test_sys.physmem.port
+    if options.checker:
+        test_sys.cpu[i].addCheckerCpu()
+
+CacheConfig.config_cache(options, test_sys)
 
 if buildEnv['TARGET_ISA'] == 'mips':
     setMipsOptions(TestCPUClass)
diff --git a/configs/example/se.py b/configs/example/se.py
index f2a26709e..09e3d69fa 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -175,15 +175,6 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
                 physmem = PhysicalMemory(range=AddrRange("512MB")),
                 membus = Bus(), mem_mode = test_mem_mode)
 
-if options.ruby:
-    options.use_map = True
-    Ruby.create_system(options, system)
-    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-else:
-    system.system_port = system.membus.slave
-    system.physmem.port = system.membus.master
-    CacheConfig.config_cache(options, system)
-
 for i in xrange(np):
     system.cpu[i].workload = multiprocesses[i]
 
@@ -194,6 +185,18 @@ for i in xrange(np):
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
 
+    if options.checker:
+        system.cpu[i].addCheckerCpu()
+
+if options.ruby:
+    options.use_map = True
+    Ruby.create_system(options, system)
+    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+else:
+    system.system_port = system.membus.slave
+    system.physmem.port = system.membus.master
+    CacheConfig.config_cache(options, system)
+
 root = Root(full_system = False, system = system)
 
 Simulation.run(options, root, system, FutureClass)