ruby: single physical memory in fs mode

Both ruby and the system used to maintain memory copies.  With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations.  This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out.  All the memory accesses now source and sink values
to the memory maintained by ruby.

6 files changed, 12 insertions, 27 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 19a2bd358..abf8fe966 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -135,7 +135,10 @@ def build_test_system(np):
             print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
             sys.exit(1)
 
-        Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
+        Ruby.create_system(options, True, test_sys, test_sys.iobus,
+                           test_sys._dma_ports)
+        test_sys.physmem = [SimpleMemory(range = r, null = True)
+                          for r in test_sys.mem_ranges]
 
         # Create a seperate clock domain for Ruby
         test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -160,13 +163,9 @@ def build_test_system(np):
                 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
                 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
 
-            test_sys.ruby._cpu_ports[i].access_phys_mem = True
-
-        # Create the appropriate memory controllers
-        # and connect them to the IO bus
-        test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
-        for i in xrange(len(test_sys.mem_ctrls)):
-            test_sys.mem_ctrls[i].port = test_sys.iobus.master
+            # Connect the ruby io port to the PIO bus,
+            # assuming that there is just one such port.
+            test_sys.iobus.master = test_sys.ruby._io_port.slave
 
     else:
         if options.caches or options.l2cache:
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 21c808459..6773aea6d 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -109,7 +109,7 @@ system.cpu = RubyDirectedTester(requests_to_complete = \
                                    options.requests,
                                    generator = generator)
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Since Ruby runs at an independent frequency, create a seperate clock
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 4e2cde791..15684d153 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -128,7 +128,7 @@ else:
 dma_ports = []
 for (i, dma) in enumerate(dmas):
     dma_ports.append(dma.test)
-Ruby.create_system(options, system, dma_ports = dma_ports)
+Ruby.create_system(options, False, system, dma_ports = dma_ports)
 
 # Create a top-level voltage domain and clock domain
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
@@ -159,12 +159,6 @@ for (i, cpu) in enumerate(cpus):
     #
     system.ruby._cpu_ports[i].deadlock_threshold = 5000000
 
-    #
-    # Ruby doesn't need the backing image of memory when running with
-    # the tester.
-    #
-    system.ruby._cpu_ports[i].access_phys_mem = False
-
 for (i, dma) in enumerate(dmas):
     #
     # Tie the dma memtester ports to the correct functional port
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index b9ca6ddf0..6e9a88431 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -113,7 +113,7 @@ system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
                                    voltage_domain = system.voltage_domain)
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a seperate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -125,8 +125,6 @@ for ruby_port in system.ruby._cpu_ports:
      # Tie the cpu test ports to the ruby cpu port
      #
      cpus[i].test = ruby_port.slave
-     ruby_port.access_phys_mem = False
-
      i += 1
 
 # -----------------------
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 63faeb97a..7cde5b86c 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -106,7 +106,7 @@ system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
                                    voltage_domain = system.voltage_domain)
 
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
 
 # Create a seperate clock domain for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -137,12 +137,6 @@ for ruby_port in system.ruby._cpu_ports:
     #
     ruby_port.using_ruby_tester = True
 
-    #
-    # Ruby doesn't need the backing image of memory when running with
-    # the tester.
-    #
-    ruby_port.access_phys_mem = False
-
 # -----------------------
 # run simulation
 # -----------------------
diff --git a/configs/example/se.py b/configs/example/se.py
index f5aef5c2f..461ebf11c 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -231,7 +231,7 @@ if options.ruby:
     system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
                               null = True)
     options.use_map = True
-    Ruby.create_system(options, system)
+    Ruby.create_system(options, False, system)
     assert(options.num_cpus == len(system.ruby._cpu_ports))
 
     system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,