config: correct example ruby scripts

A couple of recent changesets added/deleted/edited some variables
that are needed for running the example ruby scripts. This changeset
edits these scripts to bring them to a working state.

4 files changed, 18 insertions, 10 deletions

diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index fe96bdc2d..f511b0139 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -92,7 +92,8 @@ else:
 # actually used by the rubytester, but is included to support the
 # M5 memory size == Ruby memory size checks
 #
-system = System(physmem = SimpleMemory())
+system = System(physmem = SimpleMemory(),
+                mem_ranges = [AddrRange(options.mem_size)])
 
 
 # Create a top-level voltage domain and clock domain
@@ -136,6 +137,6 @@ m5.ticks.setGlobalFrequency('1ns')
 m5.instantiate()
 
 # simulate until program terminates
-exit_event = m5.simulate(options.maxtick)
+exit_event = m5.simulate(options.abs_max_tick)
 
 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index b164447f8..7848a8672 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -108,7 +108,8 @@ system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
-                clk_domain = SrcClockDomain(clock = options.sys_clock))
+                clk_domain = SrcClockDomain(clock = options.sys_clock),
+                mem_ranges = [AddrRange(options.mem_size)])
 
 if options.num_dmas > 0:
     dmas = [ MemTest(atomic = False,
@@ -129,8 +130,13 @@ for (i, dma) in enumerate(dmas):
     dma_ports.append(dma.test)
 Ruby.create_system(options, system, dma_ports = dma_ports)
 
+# Create a top-level voltage domain and clock domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+                                   voltage_domain = system.voltage_domain)
 # Create a seperate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                        voltage_domain = system.voltage_domain)
 
 #
 # The tester is most effective when randomization is turned on and
@@ -183,6 +189,6 @@ m5.ticks.setGlobalFrequency('1ns')
 m5.instantiate()
 
 # simulate until program terminates
-exit_event = m5.simulate(options.maxtick)
+exit_event = m5.simulate(options.abs_max_tick)
 
 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index 5a9764d5a..e1ec325bb 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -103,8 +103,8 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
          for i in xrange(options.num_cpus) ]
 
 # create the desired simulated system
-system = System(cpu = cpus,
-                physmem = SimpleMemory())
+system = System(cpu = cpus, physmem = SimpleMemory(),
+                mem_ranges = [AddrRange(options.mem_size)])
 
 
 # Create a top-level voltage domain and clock domain
@@ -143,6 +143,6 @@ m5.ticks.setGlobalFrequency('1ns')
 m5.instantiate()
 
 # simulate until program terminates
-exit_event = m5.simulate(options.maxtick)
+exit_event = m5.simulate(options.abs_max_tick)
 
 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 203a4b142..7a8af8b5e 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -97,7 +97,8 @@ tester = RubyTester(check_flush = check_flush,
 # actually used by the rubytester, but is included to support the
 # M5 memory size == Ruby memory size checks
 #
-system = System(tester = tester, physmem = SimpleMemory())
+system = System(tester = tester, physmem = SimpleMemory(),
+                mem_ranges = [AddrRange(options.mem_size)])
 
 # Create a top-level voltage domain and clock domain
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
@@ -156,6 +157,6 @@ m5.ticks.setGlobalFrequency('1ns')
 m5.instantiate()
 
 # simulate until program terminates
-exit_event = m5.simulate(options.maxtick)
+exit_event = m5.simulate(options.abs_max_tick)
 
 print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()