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authorEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es>2014-09-01 16:55:30 -0500
committerEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es>2014-09-01 16:55:30 -0500
commit01f792a3675983411ff77b54cbee7ffee2a3d5d5 (patch)
tree0f1d219ac9ff1d10b865d856d640884e2b177f13 /configs/example
parent5efbb4442a0e8c653539e263bf87c48849280e23 (diff)
downloadgem5-01f792a3675983411ff77b54cbee7ffee2a3d5d5.tar.xz
ruby: Fixes clock domains in configuration files
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/ruby_direct_test.py2
-rw-r--r--configs/example/ruby_random_test.py2
-rw-r--r--configs/example/se.py2
3 files changed, 4 insertions, 2 deletions
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 36314fbfb..21c808459 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -105,7 +105,7 @@ system.clk_domain = SrcClockDomain(clock = options.sys_clock,
#
# Create the ruby random tester
#
-system.tester = RubyDirectedTester(requests_to_complete = \
+system.cpu = RubyDirectedTester(requests_to_complete = \
options.requests,
generator = generator)
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 32d5cf34d..63faeb97a 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -97,7 +97,7 @@ tester = RubyTester(check_flush = check_flush,
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(tester = tester, physmem = SimpleMemory(),
+system = System(cpu = tester, physmem = SimpleMemory(),
mem_ranges = [AddrRange(options.mem_size)])
# Create a top-level voltage domain and clock domain
diff --git a/configs/example/se.py b/configs/example/se.py
index c6b98ec0e..ad15e14b5 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -235,6 +235,8 @@ if options.ruby:
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
+ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]