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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:09 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:09 -0600 |
| commit | 2208ea049f60618e432c69c065926bcbc810581a (patch) | |
| tree | dcc2c0afed74ec56969df9fa20b92655f767c158 /configs/example | |
| parent | e731cf4c1df8db0c7bcb689aba0146199a93b64e (diff) | |
| download | gem5-2208ea049f60618e432c69c065926bcbc810581a.tar.xz | |
MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.
In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 05e35c4ba..11d7d43f0 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010-2011 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -157,23 +157,19 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] CacheConfig.config_cache(options, test_sys) +if bm[0]: + mem_size = bm[0].mem() +else: + mem_size = SysConfig().mem() if options.caches or options.l2cache: - if bm[0]: - mem_size = bm[0].mem() - else: - mem_size = SysConfig().mem() - # For x86, we need to poke a hole for interrupt messages to get back to the - # CPU. These use a portion of the physical address space which has a - # non-zero prefix in the top nibble. Normal memory accesses have a 0 - # prefix. - if buildEnv['TARGET_ISA'] == 'x86': - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] - else: - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] - test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] test_sys.iocache = IOCache(addr_range=mem_size) test_sys.iocache.cpu_side = test_sys.iobus.port test_sys.iocache.mem_side = test_sys.membus.port +else: + test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [AddrRange(0, mem_size)]) + test_sys.iobridge.slave = test_sys.iobus.port + test_sys.iobridge.master = test_sys.membus.port for i in xrange(np): if options.fastmem: |