MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

3 files changed, 9 insertions, 8 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index cf3dfdb89..754a0b79b 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -160,13 +160,13 @@ else:
     mem_size = SysConfig().mem()
 if options.caches or options.l2cache:
     test_sys.iocache = IOCache(addr_range=mem_size)
-    test_sys.iocache.cpu_side = test_sys.iobus.port
-    test_sys.iocache.mem_side = test_sys.membus.port
+    test_sys.iocache.cpu_side = test_sys.iobus.master
+    test_sys.iocache.mem_side = test_sys.membus.slave
 else:
     test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
                                ranges = [AddrRange(mem_size)])
-    test_sys.iobridge.slave = test_sys.iobus.port
-    test_sys.iobridge.master = test_sys.membus.port
+    test_sys.iobridge.slave = test_sys.iobus.master
+    test_sys.iobridge.master = test_sys.membus.slave
 
 for i in xrange(np):
     if options.fastmem:
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index d7fc45bde..04b99034c 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -130,8 +130,9 @@ for (i, cpu) in enumerate(system.cpu):
     if buildEnv['TARGET_ISA'] == "x86":
         cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
         cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
-        cpu.interrupts.pio = system.piobus.port
-        cpu.interrupts.int_port = system.piobus.port
+        cpu.interrupts.pio = system.piobus.master
+        cpu.interrupts.int_master = system.piobus.slave
+        cpu.interrupts.int_slave = system.piobus.master
 
 root = Root(full_system = True, system = system)
 
diff --git a/configs/example/se.py b/configs/example/se.py
index 35025a8ff..d7b876d46 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -182,8 +182,8 @@ if options.ruby:
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 else:
-    system.system_port = system.membus.port
-    system.physmem.port = system.membus.port
+    system.system_port = system.membus.slave
+    system.physmem.port = system.membus.master
     CacheConfig.config_cache(options, system)
 
 for i in xrange(np):