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authorAndreas Hansson <andreas.hansson@arm.com>2013-01-07 13:05:38 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-01-07 13:05:38 -0500
commite65de3f5ca1d1a91265d09b1950a2d69c620631b (patch)
tree032c2483fde6e6c79e79495862f7ee5dd490ffd9 /configs/example
parent15a979c6be704a4bb083b64148d1a25d7fc4e682 (diff)
downloadgem5-e65de3f5ca1d1a91265d09b1950a2d69c620631b.tar.xz
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py7
1 files changed, 4 insertions, 3 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 9b8ae1d29..b938cb96c 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -119,11 +119,11 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
if options.caches or options.l2cache:
test_sys.iocache = IOCache(clock = '1GHz',
- addr_ranges=[test_sys.physmem.range])
+ addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
- test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range])
+ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
@@ -163,8 +163,9 @@ if len(bm) == 2:
drive_sys.cpu.fastmem = True
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
+
drive_sys.iobridge = Bridge(delay='50ns',
- ranges = [drive_sys.physmem.range])
+ ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave