summaryrefslogtreecommitdiff
path: root/configs/example
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:33 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:33 -0400
commit49d88f08b0ff463bca04285dca240b3730889a1d (patch)
treee4affba86713db0136091f1c9c25ff6e975048a9 /configs/example
parente553844efc4247f5be870fad5ea919af85858a55 (diff)
downloadgem5-49d88f08b0ff463bca04285dca240b3730889a1d.tar.xz
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py5
-rw-r--r--configs/example/ruby_fs.py4
2 files changed, 3 insertions, 6 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index ff59ca67d..bcd58ca5e 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -174,8 +174,7 @@ CacheConfig.config_cache(options, test_sys)
# Create the appropriate memory controllers and connect them to the
# memory bus
-test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
- for r in test_sys.mem_ranges]
+test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.membus.master
@@ -225,7 +224,7 @@ if len(bm) == 2:
# Create the appropriate memory controllers and connect them to the
# memory bus
- drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
+ drive_sys.mem_ctrls = [DriveMemClass(range = r)
for r in drive_sys.mem_ranges]
for i in xrange(len(drive_sys.mem_ctrls)):
drive_sys.mem_ctrls[i].port = drive_sys.membus.master
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index a254841d2..60c4be2b3 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -128,9 +128,7 @@ for (i, cpu) in enumerate(system.cpu):
# Create the appropriate memory controllers and connect them to the
# PIO bus
-system.mem_ctrls = [TestMemClass(range = r,
- conf_table_reported = True)
- for r in system.mem_ranges]
+system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
for i in xrange(len(system.physmem)):
system.mem_ctrls[i].port = system.piobus.master