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authorAndreas Hansson <andreas.hansson@arm.com>2012-09-27 08:59:25 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-09-27 08:59:25 -0400
commit6596059d058d783205f6570206c1088fad18817d (patch)
tree7e700383ae189e36c50405a0248672efeef266fe /configs/example
parent9d9b71e485a424bc09e56806cc69d14413a79a48 (diff)
downloadgem5-6596059d058d783205f6570206c1088fad18817d.tar.xz
Configs: Fix memtest cache latency to match new parameters
This patch changes the memtest config to use the new response latency of the cache model.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/memtest.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index e337fe2b1..b29a612e9 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -110,7 +110,8 @@ if len(treespec) < 1:
# define prototype L1 cache
proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
- latency = '1ns', tgts_per_mshr = 8)
+ hit_latency = '1ns', response_latency = '1ns',
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1