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authorKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
commit269259004943b80916ec9b6354f2fc00c811c88b (patch)
tree4a01b0300aef6692a787f85d42280a1dbdb086e6 /configs/example
parent422ab8bec0034a6b703578ec2c92350c6382875a (diff)
downloadgem5-269259004943b80916ec9b6354f2fc00c811c88b.tar.xz
Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py74
1 files changed, 74 insertions, 0 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 74ee875a3..0ac05338f 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -97,6 +97,8 @@ else:
if m5.build_env['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
+elif m5.build_env['TARGET_ISA'] == "mips":
+ test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "x86":
@@ -140,9 +142,81 @@ for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].physmem_port = test_sys.physmem.port
+if m5.build_env['TARGET_ISA'] == 'mips':
+ #CP0 Configuration
+ TestCPUClass.CP0_PRId_CompanyOptions = 0
+ TestCPUClass.CP0_PRId_CompanyID = 1
+ TestCPUClass.CP0_PRId_ProcessorID = 147
+ TestCPUClass.CP0_PRId_Revision = 0
+
+ #CP0 Interrupt Control
+ TestCPUClass.CP0_IntCtl_IPTI = 7
+ TestCPUClass.CP0_IntCtl_IPPCI = 7
+
+ # Config Register
+ #TestCPUClass.CP0_Config_K23 = 0 # Since TLB
+ #TestCPUClass.CP0_Config_KU = 0 # Since TLB
+ TestCPUClass.CP0_Config_BE = 0 # Little Endian
+ TestCPUClass.CP0_Config_AR = 1 # Architecture Revision 2
+ TestCPUClass.CP0_Config_AT = 0 # MIPS32
+ TestCPUClass.CP0_Config_MT = 1 # TLB MMU
+ #TestCPUClass.CP0_Config_K0 = 2 # Uncached
+
+ #Config 1 Register
+ TestCPUClass.CP0_Config1_M = 1 # Config2 Implemented
+ TestCPUClass.CP0_Config1_MMU = 63 # TLB Size
+ # ***VERY IMPORTANT***
+ # Remember to modify CP0_Config1 according to cache specs
+ # Examine file ../common/Cache.py
+ TestCPUClass.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
+ TestCPUClass.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
+ TestCPUClass.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
+ TestCPUClass.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
+ TestCPUClass.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
+ TestCPUClass.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
+ TestCPUClass.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
+ TestCPUClass.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
+ TestCPUClass.CP0_Config1_PC = 1 # Performance Counters Implemented
+ TestCPUClass.CP0_Config1_WR = 0 # Watch Registers Implemented
+ TestCPUClass.CP0_Config1_CA = 0 # Mips16e NOT implemented
+ TestCPUClass.CP0_Config1_EP = 0 # EJTag Not Implemented
+ TestCPUClass.CP0_Config1_FP = 0 # FPU Implemented
+
+ #Config 2 Register
+ TestCPUClass.CP0_Config2_M = 1 # Config3 Implemented
+ TestCPUClass.CP0_Config2_TU = 0 # Tertiary Cache Control
+ TestCPUClass.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
+ TestCPUClass.CP0_Config2_TL = 0 # Tertiary Cache Line Size
+ TestCPUClass.CP0_Config2_TA = 0 # Tertiary Cache Associativity
+ TestCPUClass.CP0_Config2_SU = 0 # Secondary Cache Control
+ TestCPUClass.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
+ TestCPUClass.CP0_Config2_SL = 0 # Secondary Cache Line Size
+ TestCPUClass.CP0_Config2_SA = 0 # Secondary Cache Associativity
+
+
+ #Config 3 Register
+ TestCPUClass.CP0_Config3_M = 0 # Config4 Not Implemented
+ TestCPUClass.CP0_Config3_DSPP = 1 # DSP ASE Present
+ TestCPUClass.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
+ TestCPUClass.CP0_Config3_VEIC = 0 # EIC Supported
+ TestCPUClass.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
+ TestCPUClass.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
+ TestCPUClass.CP0_Config3_MT = 0 # MT Not present
+ TestCPUClass.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
+ TestCPUClass.CP0_Config3_TL = 0 # TraceLogic Not implemented
+
+ #SRS Ctl - HSS
+ TestCPUClass.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
+
+
+ #TestCPUClass.tlb = TLB()
+ #TestCPUClass.UnifiedTLB = 1
+
if len(bm) == 2:
if m5.build_env['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
+ elif m5.build_env['TARGET_ISA'] == 'mips':
+ drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif m5.build_env['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif m5.build.env['TARGET_ISA'] == 'x86':