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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-06 13:46:31 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-04-06 13:46:31 -0400 |
commit | b00949d88bb3185dfa2e27799de7f90e5a449be8 (patch) | |
tree | 74789b938463bcf38d5ffd5e6be5ef7a02d84a58 /configs/example | |
parent | dbe1608fd58d818f59a0adf5f3fb562f61242f99 (diff) | |
download | gem5-b00949d88bb3185dfa2e27799de7f90e5a449be8.tar.xz |
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.
All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.
Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
Diffstat (limited to 'configs/example')
-rw-r--r-- | configs/example/memtest.py | 4 | ||||
-rw-r--r-- | configs/example/ruby_direct_test.py | 4 | ||||
-rw-r--r-- | configs/example/ruby_mem_test.py | 4 | ||||
-rw-r--r-- | configs/example/ruby_network_test.py | 2 | ||||
-rw-r--r-- | configs/example/ruby_random_test.py | 4 | ||||
-rw-r--r-- | configs/example/se.py | 2 |
6 files changed, 10 insertions, 10 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 5faee1bc7..2dcccbba6 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -140,8 +140,8 @@ for scale in treespec[:-2]: prototypes.insert(0, next) # system simulated -system = System(funcmem = PhysicalMemory(), - physmem = PhysicalMemory(latency = "100ns")) +system = System(funcmem = SimpleMemory(in_addr_map = False), + physmem = SimpleMemory(latency = "100ns")) def make_level(spec, prototypes, attach_obj, attach_port): fanout = spec[0] diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py index 53a1b6850..f591d47ea 100644 --- a/configs/example/ruby_direct_test.py +++ b/configs/example/ruby_direct_test.py @@ -83,11 +83,11 @@ else: sys.exit(1) # -# Create the M5 system. Note that the PhysicalMemory Object isn't +# Create the M5 system. Note that the Memory Object isn't # actually used by the rubytester, but is included to support the # M5 memory size == Ruby memory size checks # -system = System(physmem = PhysicalMemory()) +system = System(physmem = SimpleMemory()) # # Create the ruby random tester diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index 4b0948365..4d7932b77 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -105,8 +105,8 @@ cpus = [ MemTest(atomic = False, for i in xrange(options.num_cpus) ] system = System(cpu = cpus, - funcmem = PhysicalMemory(), - physmem = PhysicalMemory()) + funcmem = SimpleMemory(in_addr_map = False), + physmem = SimpleMemory()) if options.num_dmas > 0: dmas = [ MemTest(atomic = False, diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py index 2d68a81ea..1d44813ac 100644 --- a/configs/example/ruby_network_test.py +++ b/configs/example/ruby_network_test.py @@ -103,7 +103,7 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts, # create the desired simulated system system = System(cpu = cpus, - physmem = PhysicalMemory()) + physmem = SimpleMemory()) Ruby.create_system(options, system) diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py index 11571a297..cb6a74776 100644 --- a/configs/example/ruby_random_test.py +++ b/configs/example/ruby_random_test.py @@ -92,11 +92,11 @@ tester = RubyTester(check_flush = check_flush, wakeup_frequency = options.wakeup_freq) # -# Create the M5 system. Note that the PhysicalMemory Object isn't +# Create the M5 system. Note that the Memory Object isn't # actually used by the rubytester, but is included to support the # M5 memory size == Ruby memory size checks # -system = System(tester = tester, physmem = PhysicalMemory()) +system = System(tester = tester, physmem = SimpleMemory()) Ruby.create_system(options, system) diff --git a/configs/example/se.py b/configs/example/se.py index a2f8a09dc..853947475 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -152,7 +152,7 @@ CPUClass.numThreads = numThreads; np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], - physmem = PhysicalMemory(range=AddrRange("512MB")), + physmem = SimpleMemory(range=AddrRange("512MB")), membus = Bus(), mem_mode = test_mem_mode) # Sanity check |