factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

configs/common/Simulation.py:
    enable going from checkpoint into arbitrary CPU with or without caches.

--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2

2 files changed, 7 insertions, 24 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 67c3912ef..180cd2719 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -72,16 +72,8 @@ if args:
 DriveCPUClass = AtomicSimpleCPU
 drive_mem_mode = 'atomic'
 
-# system under test can be any of these CPUs
-if options.detailed:
-    TestCPUClass = DerivO3CPU
-    test_mem_mode = 'timing'
-elif options.timing:
-    TestCPUClass = TimingSimpleCPU
-    test_mem_mode = 'timing'
-else:
-    TestCPUClass = AtomicSimpleCPU
-    test_mem_mode = 'atomic'
+# system under test can be any CPU
+(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
 TestCPUClass.clock = '2GHz'
 DriveCPUClass.clock = '2GHz'
@@ -103,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
 np = options.num_cpus
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 for i in xrange(np):
-    if options.caches and not options.standard_switch:
+    if options.caches and not options.standard_switch and not FutureClass:
         test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                 L1Cache(size = '64kB'))
     test_sys.cpu[i].connectMemPorts(test_sys.membus)
@@ -119,4 +111,4 @@ else:
     print "Error I don't know how to create more than 2 systems."
     sys.exit(1)
 
-Simulation.run(options, root, test_sys)
+Simulation.run(options, root, test_sys, FutureClass)
diff --git a/configs/example/se.py b/configs/example/se.py
index 46f2d4a1a..0a158244f 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -88,16 +88,7 @@ if options.detailed:
             process += [smt_process, ]
             smt_idx += 1
 
-
-if options.timing:
-    CPUClass = TimingSimpleCPU
-    test_mem_mode = 'timing'
-elif options.detailed:
-    CPUClass = DerivO3CPU
-    test_mem_mode = 'timing'
-else:
-    CPUClass = AtomicSimpleCPU
-    test_mem_mode = 'atomic'
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
 CPUClass.clock = '2GHz'
 
@@ -110,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 system.physmem.port = system.membus.port
 
 for i in xrange(np):
-    if options.caches and not options.standard_switch:
+    if options.caches and not options.standard_switch and not FutureClass:
         system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                               L1Cache(size = '64kB'))
     system.cpu[i].connectMemPorts(system.membus)
@@ -118,4 +109,4 @@ for i in xrange(np):
 
 root = Root(system = system)
 
-Simulation.run(options, root, system)
+Simulation.run(options, root, system, FutureClass)