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authorAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
commit7eccb1b779cb6458ed78ba73f2fdabe94fa805b3 (patch)
treea47dc043defd5ff0afad3bdf103bc1a147dc0091 /configs/example
parentf821c5472b5e524053846bd57b83c81238be159f (diff)
downloadgem5-7eccb1b779cb6458ed78ba73f2fdabe94fa805b3.tar.xz
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4fedf12db..b17266e54 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -134,8 +134,8 @@ if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.caches or options.l2cache:
- test_sys.iocache = IOCache(clock = '1GHz',
- addr_ranges = test_sys.mem_ranges)
+ # By default the IOCache runs at the system clock
+ test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else: