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authorKevin Lim <ktlim@umich.edu>2006-10-31 14:33:56 -0500
committerKevin Lim <ktlim@umich.edu>2006-10-31 14:33:56 -0500
commitbfd5eb2b08dad700d085a637d5e16a61dcc530d7 (patch)
treed8a5404b828f37287a020ca028a4ea8fc13a106b /configs/example
parentb26355daa87c7a86a96a90b2002bc5684741288c (diff)
downloadgem5-bfd5eb2b08dad700d085a637d5e16a61dcc530d7.tar.xz
Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py4
-rw-r--r--configs/example/se.py5
2 files changed, 1 insertions, 8 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 76b62a066..26089aa16 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -137,13 +137,11 @@ for i in xrange(np):
test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
MyCache(size = '64kB'))
test_sys.cpu[i].connectMemPorts(test_sys.membus)
- test_sys.cpu[i].mem = test_sys.physmem
if len(bm) == 2:
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
- drive_sys.cpu.mem = drive_sys.physmem
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(clock = '1THz', system = test_sys)
@@ -163,8 +161,6 @@ if options.standard_switch:
switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
MyCache(size = '64kB'))
- switch_cpus[i].mem = test_sys.physmem
- switch_cpus1[i].mem = test_sys.physmem
switch_cpus[i].connectMemPorts(test_sys.membus)
root.switch_cpus = switch_cpus
root.switch_cpus1 = switch_cpus1
diff --git a/configs/example/se.py b/configs/example/se.py
index 2e63e27da..7261aeb34 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -39,7 +39,7 @@ parser = optparse.OptionParser()
# Benchmark options
parser.add_option("-c", "--cmd",
- default="../../tests/test-progs/hello/bin/alpha/linux/hello",
+ default="../tests/test-progs/hello/bin/alpha/linux/hello",
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \" around the entire\
@@ -131,7 +131,6 @@ system = System(cpu = cpu,
membus = Bus())
system.physmem.port = system.membus.port
system.cpu.connectMemPorts(system.membus)
-system.cpu.mem = system.physmem
system.cpu.clock = '2GHz'
if options.caches and not options.standard_switch:
system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'),
@@ -155,8 +154,6 @@ if options.standard_switch:
switch_cpu.workload = process
switch_cpu1.workload = process
- switch_cpu.mem = system.physmem
- switch_cpu1.mem = system.physmem
switch_cpu.connectMemPorts(system.membus)
root.switch_cpu = switch_cpu
root.switch_cpu1 = switch_cpu1