config: Update script to set cache line size on system

This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.

2 files changed, 5 insertions, 3 deletions

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index a74f4b2f3..65f3ec315 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -109,7 +109,7 @@ if len(treespec) < 1:
      sys.exit(1)
 
 # define prototype L1 cache
-proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
+proto_l1 = BaseCache(size = '32kB', assoc = 4,
                      hit_latency = '1ns', response_latency = '1ns',
                      tgts_per_mshr = 8)
 
@@ -143,7 +143,8 @@ for scale in treespec[:-2]:
 # system simulated
 system = System(funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
-                physmem = SimpleMemory(latency = "100ns"))
+                physmem = SimpleMemory(latency = "100ns"),
+                cache_line_size = block_size)
 system.clk_domain = SrcClockDomain(clock =  options.sys_clock)
 
 def make_level(spec, prototypes, attach_obj, attach_port):
diff --git a/configs/example/se.py b/configs/example/se.py
index 63f6ddc80..7b577239f 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -159,7 +159,8 @@ np = options.num_cpus
 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
                 physmem = MemClass(range=AddrRange(options.mem_size)),
                 mem_mode = test_mem_mode,
-                clk_domain = SrcClockDomain(clock = options.sys_clock))
+                clk_domain = SrcClockDomain(clock = options.sys_clock),
+                cache_line_size = options.cacheline_size)
 
 # Create a separate clock domain for the CPUs
 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)