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| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 16:45:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-03-09 16:45:47 -0500 |
| commit | d2a0db7fe971f4153fee2fbf57c550ea59c246fd (patch) | |
| tree | a0944cda22e1c05c81ecd56390a0506fcb68bb1a /configs/example | |
| parent | 470051345af2a78425730bd790000530b1b8a1f5 (diff) | |
| download | gem5-d2a0db7fe971f4153fee2fbf57c550ea59c246fd.tar.xz | |
ARM: Fix memory starting at non-zero address and exceeding max mem for a system.
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index b3d607a1b..98e5147fc 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -157,7 +157,7 @@ if bm[0]: else: mem_size = SysConfig().mem() if options.caches or options.l2cache: - test_sys.iocache = IOCache(addr_ranges=[mem_size]) + test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range]) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave else: |