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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-05-31 13:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-05-31 13:30:04 -0400 |
| commit | 0d329407116921cd9aed6f02da551cc5a8ec5131 (patch) | |
| tree | 6cc534a94543ed1e40c65d502cd428338eabb94d /configs/example | |
| parent | fb9bfb9cfcb6ef5db6881b769c7011ff4907f219 (diff) | |
| download | gem5-0d329407116921cd9aed6f02da551cc5a8ec5131.tar.xz | |
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/memtest.py | 2 | ||||
| -rw-r--r-- | configs/example/se.py | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 2dcccbba6..590378920 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -148,7 +148,7 @@ def make_level(spec, prototypes, attach_obj, attach_port): parent = attach_obj # use attach obj as config parent too if len(spec) > 1 and (fanout > 1 or options.force_bus): port = getattr(attach_obj, attach_port) - new_bus = Bus(clock="500MHz", width=16) + new_bus = CoherentBus(clock="500MHz", width=16) if (port.role == 'MASTER'): new_bus.slave = port attach_port = "master" diff --git a/configs/example/se.py b/configs/example/se.py index 8324bea4e..83abbd2f3 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -153,7 +153,7 @@ np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], physmem = SimpleMemory(range=AddrRange("512MB")), - membus = Bus(), mem_mode = test_mem_mode) + membus = CoherentBus(), mem_mode = test_mem_mode) # Sanity check if options.fastmem and (options.caches or options.l2cache): |