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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:10:54 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:10:54 -0400
commit88554790c34f6fef4ba6285927fb9742b90ab258 (patch)
tree402fe474613aea36065f773f410d431637592955 /configs/example
parentd17f5084ed93efd6bdb3ed46b2f81b9d1240af8c (diff)
downloadgem5-88554790c34f6fef4ba6285927fb9742b90ab258.tar.xz
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency. The stat blocked_cycles that actually counter in ticks is now updated to count in cycles. As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 724e32813..ddba8554a 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -122,7 +122,8 @@ if bm[0]:
else:
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
- test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
+ test_sys.iocache = IOCache(clock = '1GHz',
+ addr_ranges=[test_sys.physmem.range])
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else: