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authorAndreas Hansson <andreas.hansson@arm.com>2016-02-10 04:08:25 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-02-10 04:08:25 -0500
commit92f021cbbed84bc1d8ceee80b78fb9be1086819c (patch)
treed65dbb57bc3443e0cd19f30012c43d268f428c63 /configs/example
parentf84ee031ccdb63d016c6f55b578085a2e5af4a4b (diff)
downloadgem5-92f021cbbed84bc1d8ceee80b78fb9be1086819c.tar.xz
mem: Move the point of coherency to the coherent crossbar
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/memtest.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index a3298890b..97bf79dff 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -299,6 +299,7 @@ make_cache_level(cachespec, cache_proto, len(cachespec), None)
# Connect the lowest level crossbar to the memory
last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
last_subsys.xbar.master = system.physmem.port
+last_subsys.xbar.point_of_coherency = True
root = Root(full_system = False, system = system)
if options.atomic: