config: Enable elastic trace capture and replay in se/fs

This patch adds changes to the configuration scripts to support elastic
tracing and replay.

The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.

The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.

3 files changed, 136 insertions, 0 deletions

diff --git a/configs/example/etrace_replay.py b/configs/example/etrace_replay.py
new file mode 100644
index 000000000..e39024f0f
--- /dev/null
+++ b/configs/example/etrace_replay.py
@@ -0,0 +1,119 @@
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Radhika Jagtap
+
+# Basic elastic traces replay script that configures a Trace CPU
+
+import optparse
+
+from m5.util import addToPath, fatal
+
+addToPath('../common')
+
+import Options
+import Simulation
+import CacheConfig
+import MemConfig
+from Caches import *
+
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+
+if '--ruby' in sys.argv:
+    print "This script does not support Ruby configuration, mainly"\
+    " because Trace CPU has been tested only with classic memory system"
+    sys.exit(1)
+
+(options, args) = parser.parse_args()
+
+if args:
+    print "Error: script doesn't take any positional arguments"
+    sys.exit(1)
+
+numThreads = 1
+
+if options.cpu_type != "trace":
+    fatal("This is a script for elastic trace replay simulation, use "\
+            "--cpu-type=trace\n");
+
+if options.num_cpus > 1:
+    fatal("This script does not support multi-processor trace replay.\n")
+
+# In this case FutureClass will be None as there is not fast forwarding or
+# switching
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
+CPUClass.numThreads = numThreads
+
+system = System(cpu = CPUClass(cpu_id=0),
+                mem_mode = test_mem_mode,
+                mem_ranges = [AddrRange(options.mem_size)],
+                cache_line_size = options.cacheline_size)
+
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system. This is used as the clock period for
+# xbar and memory
+system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
+                                   voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
+# is actually used only by the caches connected to the CPU.
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+                                       voltage_domain =
+                                       system.cpu_voltage_domain)
+
+# All cpus belong to a common cpu_clk_domain, therefore running at a common
+# frequency.
+for cpu in system.cpu:
+    cpu.clk_domain = system.cpu_clk_domain
+
+# Assign input trace files to the Trace CPU
+system.cpu.instTraceFile=options.inst_trace_file
+system.cpu.dataTraceFile=options.data_trace_file
+
+# Configure the classic memory system options
+MemClass = Simulation.setMemClass(options)
+system.membus = SystemXBar()
+system.system_port = system.membus.slave
+CacheConfig.config_cache(options, system)
+MemConfig.config_mem(options, system)
+
+root = Root(full_system = False, system = system)
+Simulation.run(options, root, system, FutureClass)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 69b2e970a..dddb2ea3c 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -214,6 +214,17 @@ def build_test_system(np):
                 test_sys.cpu[i].addCheckerCpu()
             test_sys.cpu[i].createThreads()
 
+        # If elastic tracing is enabled when not restoring from checkpoint and
+        # when not fast forwarding using the atomic cpu, then check that the
+        # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
+        # passes then attach the elastic trace probe.
+        # If restoring from checkpoint or fast forwarding, the code that does this for
+        # FutureCPUClass is in the Simulation module. If the check passes then the
+        # elastic trace probe is attached to the switch CPUs.
+        if options.elastic_trace_en and options.checkpoint_restore == None and \
+            not options.fast_forward:
+            CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
+
         CacheConfig.config_cache(options, test_sys)
 
         MemConfig.config_mem(options, test_sys)
diff --git a/configs/example/se.py b/configs/example/se.py
index 0928482b7..1b3458709 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -58,6 +58,7 @@ import Options
 import Ruby
 import Simulation
 import CacheConfig
+import CpuConfig
 import MemConfig
 from Caches import *
 from cpu2000 import *
@@ -196,6 +197,11 @@ system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
                                        voltage_domain =
                                        system.cpu_voltage_domain)
 
+# If elastic tracing is enabled, then configure the cpu and attach the elastic
+# trace probe
+if options.elastic_trace_en:
+    CpuConfig.config_etrace(CPUClass, system.cpu, options)
+
 # All cpus belong to a common cpu_clk_domain, therefore running at a common
 # frequency.
 for cpu in system.cpu: