config: remove ruby_fs.py

The patch removes the ruby_fs.py file.  The functionality is being moved to
fs.py.  This would being ruby fs simulations in line with how ruby se
simulations are started (using --ruby option).  The alpha fs config functions
are being combined for classing and ruby memory systems.  This required
renaming the piobus in ruby to iobus.  So, we will have stats being renamed
in the stats file for ruby fs regression.

3 files changed, 82 insertions, 174 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index f53f5f151..7bc044647 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -10,6 +10,8 @@
 # unmodified and in its entirety in all distributions of the software,
 # modified or unmodified, in source code or in binary form.
 #
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -37,6 +39,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Ali Saidi
+#          Brad Beckmann
 
 import optparse
 import sys
@@ -47,6 +50,9 @@ from m5.objects import *
 from m5.util import addToPath, fatal
 
 addToPath('../common')
+addToPath('../ruby')
+
+import Ruby
 
 from FSConfig import *
 from SysPaths import *
@@ -61,6 +67,10 @@ parser = optparse.OptionParser()
 Options.addCommonOptions(parser)
 Options.addFSOptions(parser)
 
+# Add the ruby specific and protocol specific options
+if '--ruby' in sys.argv:
+    Ruby.define_options(parser)
+
 (options, args) = parser.parse_args()
 
 if args:
@@ -104,13 +114,14 @@ else:
 np = options.num_cpus
 
 if buildEnv['TARGET_ISA'] == "alpha":
-    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
+    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
 elif buildEnv['TARGET_ISA'] == "mips":
     test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "sparc":
     test_sys = makeSparcSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "x86":
-    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
+    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
+            options.ruby)
 elif buildEnv['TARGET_ISA'] == "arm":
     test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
                              options.dtb_filename,
@@ -120,6 +131,9 @@ elif buildEnv['TARGET_ISA'] == "arm":
 else:
     fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
 
+# Set the cache line size for the entire system
+test_sys.cache_line_size = options.cacheline_size
+
 # Create a top-level voltage domain
 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 
@@ -156,32 +170,72 @@ test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
     test_sys.vm = KvmVM()
 
-if options.caches or options.l2cache:
-    # By default the IOCache runs at the system clock
-    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
-    test_sys.iocache.cpu_side = test_sys.iobus.master
-    test_sys.iocache.mem_side = test_sys.membus.slave
+if options.ruby:
+    # Check for timing mode because ruby does not support atomic accesses
+    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
+        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
+        sys.exit(1)
+
+    Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
+
+    # Create a seperate clock domain for Ruby
+    test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+                                    voltage_domain = test_sys.voltage_domain)
+
+    for (i, cpu) in enumerate(test_sys.cpu):
+        #
+        # Tie the cpu ports to the correct ruby system ports
+        #
+        cpu.clk_domain = test_sys.cpu_clk_domain
+        cpu.createThreads()
+        cpu.createInterruptController()
+
+        cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+        cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+
+        if buildEnv['TARGET_ISA'] == "x86":
+            cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+            cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+
+            cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
+            cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
+            cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
+
+        test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
+    # Create the appropriate memory controllers and connect them to the
+    # PIO bus
+    test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
+    for i in xrange(len(test_sys.mem_ctrls)):
+        test_sys.mem_ctrls[i].port = test_sys.iobus.master
+
 else:
-    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
-    test_sys.iobridge.slave = test_sys.iobus.master
-    test_sys.iobridge.master = test_sys.membus.slave
-
-# Sanity check
-if options.fastmem:
-    if TestCPUClass != AtomicSimpleCPU:
-        fatal("Fastmem can only be used with atomic CPU!")
-    if (options.caches or options.l2cache):
-        fatal("You cannot use fastmem in combination with caches!")
-
-for i in xrange(np):
-    if options.fastmem:
-        test_sys.cpu[i].fastmem = True
-    if options.checker:
-        test_sys.cpu[i].addCheckerCpu()
-    test_sys.cpu[i].createThreads()
+    if options.caches or options.l2cache:
+        # By default the IOCache runs at the system clock
+        test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
+        test_sys.iocache.cpu_side = test_sys.iobus.master
+        test_sys.iocache.mem_side = test_sys.membus.slave
+    else:
+        test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
+        test_sys.iobridge.slave = test_sys.iobus.master
+        test_sys.iobridge.master = test_sys.membus.slave
 
-CacheConfig.config_cache(options, test_sys)
-MemConfig.config_mem(options, test_sys)
+    # Sanity check
+    if options.fastmem:
+        if TestCPUClass != AtomicSimpleCPU:
+            fatal("Fastmem can only be used with atomic CPU!")
+        if (options.caches or options.l2cache):
+            fatal("You cannot use fastmem in combination with caches!")
+
+    for i in xrange(np):
+        if options.fastmem:
+            test_sys.cpu[i].fastmem = True
+        if options.checker:
+            test_sys.cpu[i].addCheckerCpu()
+        test_sys.cpu[i].createThreads()
+
+    CacheConfig.config_cache(options, test_sys)
+    MemConfig.config_mem(options, test_sys)
 
 if len(bm) == 2:
     if buildEnv['TARGET_ISA'] == 'alpha':
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
deleted file mode 100644
index cd45ee8af..000000000
--- a/configs/example/ruby_fs.py
+++ /dev/null
@@ -1,146 +0,0 @@
-# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-#
-# Full system configuraiton for ruby
-#
-
-import optparse
-import sys
-
-import m5
-from m5.defines import buildEnv
-from m5.objects import *
-from m5.util import addToPath, fatal
-
-addToPath('../common')
-addToPath('../ruby')
-addToPath('../topologies')
-
-import Ruby
-
-from FSConfig import *
-from SysPaths import *
-from Benchmarks import *
-import Options
-import Simulation
-
-parser = optparse.OptionParser()
-Options.addCommonOptions(parser)
-Options.addFSOptions(parser)
-
-# Add the ruby specific and protocol specific options
-Ruby.define_options(parser)
-
-(options, args) = parser.parse_args()
-options.ruby = True
-
-if args:
-    print "Error: script doesn't take any positional arguments"
-    sys.exit(1)
-
-if options.benchmark:
-    try:
-        bm = Benchmarks[options.benchmark]
-    except KeyError:
-        print "Error benchmark %s has not been defined." % options.benchmark
-        print "Valid benchmarks are: %s" % DefinedBenchmarks
-        sys.exit(1)
-else:
-    bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
-
-# Check for timing mode because ruby does not support atomic accesses
-if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
-    print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
-    sys.exit(1)
-(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-
-TestMemClass = Simulation.setMemClass(options)
-
-if buildEnv['TARGET_ISA'] == "alpha":
-    system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
-elif buildEnv['TARGET_ISA'] == "x86":
-    system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
-    Simulation.setWorkCountOptions(system, options)
-else:
-    fatal("incapable of building non-alpha or non-x86 full system!")
-system.cache_line_size = options.cacheline_size
-
-# Create a top-level voltage domain and clock domain
-system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
-
-system.clk_domain = SrcClockDomain(clock = options.sys_clock,
-                                   voltage_domain = system.voltage_domain)
-
-if options.kernel is not None:
-    system.kernel = binary(options.kernel)
-
-if options.script is not None:
-    system.readfile = options.script
-
-system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
-
-# Create a source clock for the CPUs and set the clock period
-system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
-                                       voltage_domain = system.voltage_domain)
-
-Ruby.create_system(options, system, system.piobus, system._dma_ports)
-
-# Create a seperate clock domain for Ruby
-system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
-                                        voltage_domain = system.voltage_domain)
-
-for (i, cpu) in enumerate(system.cpu):
-    #
-    # Tie the cpu ports to the correct ruby system ports
-    #
-    cpu.clk_domain = system.cpu_clk_domain
-    cpu.createThreads()
-    cpu.createInterruptController()
-
-    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
-    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
-
-    if buildEnv['TARGET_ISA'] == "x86":
-        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
-        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
-
-        cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
-        cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
-        cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
-
-    system.ruby._cpu_ruby_ports[i].access_phys_mem = True
-
-# Create the appropriate memory controllers and connect them to the
-# PIO bus
-system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
-for i in xrange(len(system.mem_ctrls)):
-    system.mem_ctrls[i].port = system.piobus.master
-
-root = Root(full_system = True, system = system)
-Simulation.run(options, root, system, FutureClass)
diff --git a/configs/example/se.py b/configs/example/se.py
index 97ad2c7de..34a3f045e 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -53,7 +53,6 @@ from m5.util import addToPath, fatal
 
 addToPath('../common')
 addToPath('../ruby')
-addToPath('../topologies')
 
 import Options
 import Ruby
@@ -145,7 +144,8 @@ if options.bench:
                         app, options.spec_input))
             multiprocesses.append(workload.makeLiveProcess())
         except:
-            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
+            print >>sys.stderr, "Unable to find workload for %s: %s" % (
+                    buildEnv['TARGET_ISA'], app)
             sys.exit(1)
 elif options.cmd:
     multiprocesses, numThreads = get_processes(options)