summaryrefslogtreecommitdiff
path: root/configs/example
diff options
context:
space:
mode:
authorDam Sunwoo <dam.sunwoo@arm.com>2013-04-22 13:20:31 -0400
committerDam Sunwoo <dam.sunwoo@arm.com>2013-04-22 13:20:31 -0400
commit2c1e34431326381833de289b1d90f2427ba16c98 (patch)
tree2f1b7a0e9a400d5b5d660b4386d4b993cbd0e31c /configs/example
parent121b15a54da77ef77e98ff59621e1c5b0f1f1f52 (diff)
downloadgem5-2c1e34431326381833de289b1d90f2427ba16c98.tar.xz
cpu: generate SimPoint basic block vector profiles
This patch is based on http://reviews.m5sim.org/r/1474/ originally written by Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout folder) based on start and end addresses of basic blocks. Some comments to the original patch are addressed and hooks are added to create and resume from checkpoints based on instruction counts dictated by external SimPoint analysis tools. SimPoint creation/resuming options will be implemented as a separate patch.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/se.py11
1 files changed, 11 insertions, 0 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 20149cccd..a5f0204fd 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -166,6 +166,13 @@ if options.fastmem:
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
+if options.simpoint_profile:
+ if not options.fastmem:
+ # Atomic CPU checked with fastmem option already
+ fatal("SimPoint generation should be done with atomic cpu and fastmem")
+ if np > 1:
+ fatal("SimPoint generation not supported with more than one CPUs")
+
for i in xrange(np):
if options.smt:
system.cpu[i].workload = multiprocesses
@@ -177,6 +184,10 @@ for i in xrange(np):
if options.fastmem:
system.cpu[i].fastmem = True
+ if options.simpoint_profile:
+ system.cpu[i].simpoint_profile = True
+ system.cpu[i].simpoint_interval = options.simpoint_interval
+
if options.checker:
system.cpu[i].addCheckerCpu()