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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-15 20:11:06 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-15 20:11:06 -0700 |
| commit | 884807a68ad7e4f390660b3becfe4ee094334e95 (patch) | |
| tree | 4c7ceec3944234c8cd983c72308115df55450dc5 /configs/example | |
| parent | f790f34fe30aaca22b829104a8cf3f547624132a (diff) | |
| download | gem5-884807a68ad7e4f390660b3becfe4ee094334e95.tar.xz | |
Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work. Timing is closer but not there yet.
--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/memtest.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index af100c9a9..5bb874e85 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -144,7 +144,7 @@ system = System(funcmem = PhysicalMemory(), def make_level(spec, prototypes, attach_obj, attach_port): fanout = spec[0] parent = attach_obj # use attach obj as config parent too - if fanout > 1 or options.force_bus: + if len(spec) > 1 and (fanout > 1 or options.force_bus): new_bus = Bus(clock="500MHz", width=16) new_bus.port = getattr(attach_obj, attach_port) parent.cpu_side_bus = new_bus |