Added fastmem option.

Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c

2 files changed, 8 insertions, 0 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index ca1408970..3a57fe5b8 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -132,6 +132,9 @@ for i in xrange(np):
     else:
         test_sys.cpu[i].connectMemPorts(test_sys.membus)
 
+    if options.fastmem:
+        test_sys.cpu[i].physmem_port = test_sys.physmem.port
+
 if len(bm) == 2:
     if m5.build_env['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
@@ -139,6 +142,8 @@ if len(bm) == 2:
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
     drive_sys.cpu.connectMemPorts(drive_sys.membus)
+    if options.fastmem:
+        drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
 
diff --git a/configs/example/se.py b/configs/example/se.py
index 20fe75a21..639bcd7c6 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -114,6 +114,9 @@ for i in xrange(np):
         system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
+    if options.fastmem:
+        system.cpu[0].physmem_port = system.physmem.port
+
 root = Root(system = system)
 
 Simulation.run(options, root, system, FutureClass)