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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 29c45ccd2322470d0d6cef0ae20600c8c68f97e9 (patch) | |
| tree | ec62739567ba7d442c8b65550507cdab6b7827dc /configs/example | |
| parent | 8e5c441a54b481085d6311f14af66e41b5766f91 (diff) | |
| download | gem5-29c45ccd2322470d0d6cef0ae20600c8c68f97e9.tar.xz | |
ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.
These changes fix the latency mismatch.
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/ruby_se.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/ruby_se.py b/configs/example/ruby_se.py index a0e839bae..d51f92f19 100644 --- a/configs/example/ruby_se.py +++ b/configs/example/ruby_se.py @@ -143,7 +143,7 @@ assert(options.timing) assert(test_mem_mode == 'timing') assert(FutureClass == None) -CPUClass.clock = '1GHz' +CPUClass.clock = options.clock np = options.num_cpus |