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authorRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:36:26 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-20 13:36:26 -0400
commitad783962c5e9ab5ee69e8b42d6c1385ef9a3b42f (patch)
treeb687dcbb275658c7aeb962f78187366688cc5eeb /configs/example
parent316e0fa8792a602bff0ee125ef78fc8e080024fa (diff)
downloadgem5-ad783962c5e9ab5ee69e8b42d6c1385ef9a3b42f.tar.xz
Give physical memory some latency to stress the system
--HG-- extra : convert_revision : 3ca32ff9140770d0774cac5e82807a0574db09dd
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/memtest.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index ae2bf5b55..141ecfd8e 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -85,7 +85,7 @@ else:
for i in xrange(options.numtesters) ]
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
- physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
+ physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16))
# l2cache & bus
if options.caches: