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authorGabe Black <gblack@eecs.umich.edu>2011-02-03 20:56:27 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-03 20:56:27 -0800
commitfd2670773195378d2a91a47365ade97e917394f2 (patch)
treea2d731cc849c1c9ddd5c62eb2bb7ab18ff568fb2 /configs/example
parent00f24ae92c7b9aa73e12fd8160b5756e80126db2 (diff)
downloadgem5-fd2670773195378d2a91a47365ade97e917394f2.tar.xz
Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py9
1 files changed, 8 insertions, 1 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 6568f4c89..1a052e282 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -153,7 +153,14 @@ if options.caches or options.l2cache:
mem_size = bm[0].mem()
else:
mem_size = SysConfig().mem()
- test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+ # For x86, we need to poke a hole for interrupt messages to get back to the
+ # CPU. These use a portion of the physical address space which has a
+ # non-zero prefix in the top nibble. Normal memory accesses have a 0
+ # prefix.
+ if buildEnv['TARGET_ISA'] == 'x86':
+ test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
+ else:
+ test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
test_sys.iocache = IOCache(addr_range=mem_size)
test_sys.iocache.cpu_side = test_sys.iobus.port